The present invention relates to a method of manufacture of a semiconductor device, and to the semiconductor device. More particularly, it relates to a method of forming a capacitor in conjunction with a semiconductor device.
In recent years, with the trend toward smaller size, lower power consumption, and higher integration of a semiconductor device, the operating voltage of a semiconductor device has become increasingly lower, and the voltage supplied from an external power source has become increasingly lower. Under such circumstances, a semiconductor device is typically equipped with a booster circuit, such as a charge pump circuit, for generating the operating voltage needed by the semiconductor device from the external power supply voltage. This kind of booster circuit includes a capacitor (capacitive element) which is formed of, for example, a MIS capacitive element utilizing a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as the capacitor.
Japanese Unexamined Patent Publication No. 2001-85633 (hereinafter referred to as the first example) discloses the following technology: In a semiconductor device having a nonvolatile memory, the capacitance of a capacitor of a charge pump circuit is formed such that a first capacitance between a first gate and a second gate and a second capacitance between the first gate and a well region are connected in parallel to each other. As a result, the area of the charge pump circuit is reduced.
Japanese Unexamined Patent Publication No. Hei 11 (1999)-251547 (hereinafter referred to as the second example) discloses the following technology: A first trench capacitor is formed which constitutes the memory cell of a DRAM (Dynamic Random Access Memory), and a second trench capacitor, having almost the same configuration as that of the first trench capacitor, is formed in another region. The second trench capacitor is also used as a capacitor in a region other than that of the DRAM.
Japanese Unexamined Patent Publication No. 2002-222924 (hereinafter referred to as the third example) discloses a technology for simultaneously forming a trench for element isolation and a desired pattern in a region where a capacitive element is formed in a semiconductor substrate.